Principal Digital Design Engineer - 14 yrs

Job Title- Principal Digital Design Engineer 

Exp- 15+yrs 

location - Bangalore  

Key Responsibilities 

 

·        Lead RTL design and development of complex IPs and subsystems within MCU SoCs, ensuring compliance with performance, power, and area (PPA) targets 

·        Drive micro-architecture definition and high-level digital design for assigned blocks 

·        Support SoC integration, delivering high-quality subsystem views and documentation to Back-end and Design Verification teams 

·        Own design quality checks, including lint, CDC, and RDC, and actively support functional verification of assigned blocks 

·        Collaborate closely with system architects, verification engineers, physical design teams, and software teams to define specifications and ensure seamless end-to-end integration 

·        Provide technical guidance and mentorship to junior engineers, raising overall team capability and design quality 

·        Contribute to continuous improvement of RTL design methodologies, coding guidelines, and design processes 

 

Qualifications 


 

Required Qualifications 

 

·        Bachelor’s degree in Electronics & Communication Engineering, Electrical Engineering, Computer Engineering, or related technical field 

·        Minimum of 15 years of hands-on experience in digital IC/ASIC design, with a strong track record of delivering high-quality silicon 

·        Strong expertise in RTL design using Verilog/VHDL 

·        Solid understanding of digital design principles, timing analysis, clocking, resets, and verification methodologies 

·        Experience using industry-standard EDA tools for synthesis, simulation, and static timing analysis 

·        Strong problem-solving skills with the ability to own blocks end-to-end 

Preferred Qualifications 

 

·        Experience owning complex IPs or subsystem designs in large SoCs 

·        Strong background in micro-architecture design and high-level digital design 

·        Hands-on experience with RTL quality tools such as Spyglass (Lint, CDC, RDC) 

·        Experience with low-power design techniques and methodologies 

·        Familiarity with SoC-level design and integration 

·        Understanding of synthesis flows and timing constraints 

·        Scripting experience in Shell, Perl, Python or use of AI for design is a strong plus.