About the role

Principal Firmware/Middleware Engineer

EXP- 15+

Location Bangalore

Please review the screening questions; based on the answers, you can share the profile

## Technical Screening Questions

1. Firmware Development:

How many years of hands-on experience do you have in low-level firmware development using C/C++, particularly bare-metal and RTOS environments .

2. Device Drivers & Virtualization:

What is your experience in developing device drivers, kernel-level software, or virtualization technologies?

3. Python & Hardware Automation:

How have you used Python for hardware automation, firmware validation, simulation/modeling,

4. High-Speed Protocols:

Which high-speed protocols have you worked on hands-on—such as PCIe Gen5/Gen6, CXL, NVLink, UALink, Ethernet, InfiniBand, etc.?

5. Network Infrastructure & Switching:

experience with network infrastructure, switching, routing, flow control, credit-based mechanisms, SerDes/PHY, or congestion management. Have you worked on any switch ASIC, accelerator fabric, server interconnect, or data-center networking products?

Job description

As the Principal Firmware Architect for UALink Switch Products, you will serve as the technical visionary responsible for defining, designing, and driving the end-to-end embedded software and firmware architecture for our next-generation AI cluster scale-up switches.

In this high-impact role, you will bridge the gap between cutting-edge silicon (ASICs) and upper-layer cluster orchestration software. You will define how firmware manages complex scale-up topologies, ensures raw hardware performance (maximizing bandwidth and minimizing latency), and maintains absolute reliability across thousands of connected AI accelerators.

1. Architectural Definition & Design

Fabric Firmware Architecture: Architect and specify the low-level firmware running on internal microcontrollers within the UALink Switch ASIC.
Hardware-Software Co-Design: Collaborate heavily with ASIC design, logic design (RTL), and verification teams to define hardware-software interfaces, registers, scratchpads, and memory maps.
Protocol Implementation: Define the firmware stack to support UALink physical, link, and transport layers, managing credits, routing tables, and flow control.

2. Initialization, Boot, & Fabric Management

Link Initialization & Training: Design deterministic, fast link-training state machines to bring up ultra-high-speed die-to-die and chassis-to-chassis UALink connections.
Topology Discovery & Routing: Architect efficient algorithms for runtime topology discovery, dynamic routing, and credit management to prevent fabric congestion.
Platform Orchestration: Lead the design of SDKs and APIs that expose switch functionality to baseboard management controllers (BMCs) using OpenBMC and Redfish APIs.

3. Performance, RAS, & Security

Latency & Bandwidth Optimization: Fine-tune bare-metal execution paths to guarantee deterministic low latency for collective communication primitives (e.g., All-Reduce, All-to-All).
Advanced RAS (Reliability, Availability, Serviceability): Design robust error-handling, telemetry, and fault-isolation micro-architectures (e.g., link degradation fallback, FEC, and error containment).
Security & Root of Trust: Implement secure boot, cryptographic firmware authentication, and runtime attestation to ensure fabric integrity.

Qualifications

Education & Experience

Degree: Bachelor’s or Master’s/Ph.D. in Computer Engineering, Electrical Engineering, Computer Science, or a related discipline.
Experience: 15+ years of hands-on experience in embedded systems, server platform architecture, or low-level silicon firmware development.

Technical Skill Set

Language Masteries: Expert-level proficiency in C for bare-metal and RTOS environments (e.g., ThreadX, FreeRTOS, Zephyr) and Python for hardware automation and modeling.
Protocol Expertise: Deep technical understanding of high-speed scale-up/scale-out interconnect protocols (UALink, NVLink, CXL, or PCIe Gen5/Gen6).
Network Switching Concepts: Comprehensive knowledge of credit-based flow control, packet routing, physical layer (PHY) equalization, and SerDes management.
Tooling: Strong familiarity with hardware debuggers (JTAG, Lauterbach Lauterbach/TRACE32) and lab equipment (Oscilloscopes, PCIe/Protocol Analyzers).