Senior Staff Engineer Design-STA Synthesis Full Chip

Senior Staff Engineer Design- STA Synthesis, Full Chip, Timing Closure

Location- Bengaluru

Your Role
Key responsibilities in your new role
 

• Develop and implement high-performance, low-power, and area-efficient digital designs for ASICs and SoCs using industry-standard EDA tools
• Work closely with design teams to understand the requirements and constraints of the design, and provide feedback on design feasibility,timing and power
• Write and implement block level and top-level constraints for synthesis, perform timing closure and power analysis
• Develop and implement synthesis flows and methodologies, and driveimprovements in the design process
• Debug and resolve design issues related to synthesis, timing, power, and area
• Understanding of DFT flows, including scan insertion and ATPG
• Optimize designs for power,performance, are and meet design goals within the given schedule
• Implement pipelining at different levels for performance optimization and timing closure
• Perform power analysis and optimize designs for low power

Your Profile
Qualifications and skills to help you succeed

• B.Tech/M.Tech in Electronics or related field with 8+ years of relevant experience
• Strong fundamentals in Synthesis and STA, with hands-on experience in timing sign-off, margin calculations, and leading STA for full-chip projects
• Expertise in MCMM analysis, multi-power domain designs, constraint mode merging, and STA flow development with bottleneck identification
• Proficient in SDC constraints, timing ECO generation, and driving TAT reduction across complex designs
• Experience collaborating closely with Design and Physical Design teams to meet aggressive schedules
• Skilled in Synopsys/Cadence EDA tools, with scripting knowledge in Tcl/Perl as an added advantage
• Strong analytical, communication, and mentoring skills with ability to work across cross-functional and global teams.
• Proficient with EDA tools from Synopsys/Cadence/Mentor

Skills- System on Chip, +STA, Synthesis, Full Chip, Timing Closure