Principal Asic RTL Design- 10+yrs

Job Title- Principal Engineer, ASIC Digital Design

Location - Bangalore  

Position Description:

• To be part of a highly skilled and challenging high speed PHY design team working on the latest technology nodes (5nm and below).
• Define the digital architecture and microarchitecture of the IP’s and its sub functions
• Responsible for all aspects of digital design from specification to silicon along with its integration with SoC.
• Active involvement in problem solving and implementing opportunities for improvement.
• Driving innovation and develop new architectures for best-in-class solution
• Mentoring and coaching other design team members on technical issues
• Pair with similar domain specialists across other geographical locations on core technical initiatives
• Pair with Analog designers to ensure smooth interface between Digital and Analog circuits
• Equal opportunity position with excellent pay package!

SKILLS required:

• Experience in end of end ownership of digital design of at least one of the ONFI, DDR, LPDDR, MIPI or PCIe PHY OR similar IP from specifications to silicon
• Experience of silicon bring and debug of aforesaid IPs
• Experience of leading a team of digital designers and collaborating with verification and physical design engineers
• Strong fundamental knowledge for Verilog and scripting languages, timing closure, DFT, Synthesis, Lint & CDC
• Strong knowledge of Asynchronous domain transfer schemes, cores, APB/JTAG
• Working knowledge of RTL2GDS flows
• Experience of working with Analog team for Mixed signal data paths
• Experience in leading R&D and future technology development projects.
• The position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams.
• Team leadership experience, including planning and managing tasks is desirable
• M.S./MTech, BS/BE (Electronics)
• Experience Required : 10+ Years