IP & Soc RTL Design

IP & Soc RTL Design 

Location:- Hyderabad

Experience:- 7+Years

Key Responsibilities

Own end‑to‑end IP and SOC development from micro‑architecture through RTL compose, integration, and physical hardware assistance. Own IP and Subsystem design from scratch, ensuring high‑quality, reusable RTL. Drive SoC integration, including CDC, lint, synthesis, STA, and power analysis. Define and review module interfaces and system‑level architecture. Collaborate closely with Architecture, Verification, FW, DFT, Synthesis, and Physical Design teams. Support post‑silicon debug and bring‑up activities. Provide technical mentorship and participate in design and methodology reviews.

 

This role is expected to utilize Micron-approved AI tools and AI-enabled workflows to improve engineering productivity, design quality, automation, and decision-making across the SoC development lifecycle. The engineer will apply AI-assisted solutions for design analysis, documentation, coding, debug, and workflow optimization while ensuring compliance with Micron AI governance standards.

 

Required Qualifications

7+ years of hands‑on IP & SoC RTL design experience. Strong expertise in micro‑architecture, Verilog/System Verilog, and RTL integration. Solid knowledge of asynchronous design concepts and CDC methodologies. Deep understanding of SoC design flows (Lint, CDC, Synthesis/STA, Power). Strong fundamentals in digital design and scripting languages. Excellent problem‑solving and communication skills. Ability to work effectively with global multi-functional teams.

 

Preferred / Added Advantages

Exposure to LPDDR Subsystem, CPU Subsystems, and SoC Test Controller design. Experience with ASIC controllers for storage or memory systems. Hands‑on post‑silicon debug and silicon support experience.