Verification Engineer

    Experience:- 5+Years 

 JOB DESCRIPTION  

• Electronic Engineering/Computer Engineering degree with 8-12 years of progressive experience in digital design and verification.
• Should have demonstrated experience in developing UVM-based testbench infrastructure from ground up, functional cover point development, code coverage analysis/closure and assertion development.
• Experience on both IP and SoC level verification with knowledge of bringing up gate level simulations.
• Experience in Power aware simulations or Formal Verification is desirable.
• Proficiency in scripting languages and utilities including Makefile, Python, Perl etc.
• Experience collaborating with product development groups spread across the globe is a must; should have strong interpersonal and communication skills.
• Mentoring junior engineers and leading block or subsystem level verification.

Responsibilities 

• Verification of key digital blocks in differentiated mixed signal SOCs targeted for the consumer market
• Complete verification ownership – Testbench Architecture, Testplan and Testbench Development, Functional Coverage Closure and Code Coverage Closure
• Usage of industry standard methodologies like UVM and constrained random approach to achieve verification goals
• Actively explore and deploy ML techniques to achieve faster turnaround time
• Debug efficiently and clearly articulate gating issues to engineering leads.
• Integrate the block level testbench at SOC level and verify SOC integration
• Actively participate in post-silicon activities such as silicon bring-up, evaluation support, ATE pattern bring-up to take SoC into production.
• Technically mentor and guide junior verification engineers on SoC Verification.